The invention relates to phase alignment of clock signals operating at nearly equal frequencies.
A variety of means and procedures for compensation or correction of drift between oscillators operating at nearly the same frequency are known. For example in U.S. Pat. No. 4,290,022 of Puckette, a phase shifter detects and corrects for phase difference between a pair of square wave of equal frequency. Phase correction is provided by selective imposition of a variable amount of delay on one of the signals, based upon the difference in phase between it and the other signal No provision, however, is made for "closing the loop" between the corrected signal and the phase detection function in such manner as to support virtually continuously variable phase correction.
Digital phase correction in the prior art finds its most varied expression in data synchronization. For example, U.S. Pat. No. 3,505,478 of Kaneko and U.S. Pat. No. 4,524,448 of Hullwegen both teach synchronization of a clock extracted from data received in a transmission channel to a local clock which is used by a data receiving unit to control local data receiving and decoding operations. In these references, one reference clock signal is extracted from transmitted data. In both patents, a variable delay unit is provided for inserting more or less delay into the received data signal before a reference clock signal is extracted from it. The Hullwegen patent shows closure of a loop in such a manner as to provide for continuous phase correction by a single loop which operates in response to the phase between the clock extracted from the data and the local clock. The Hullwegen circuit does not operate by directly correcting the phase of the clock; rather, it corrects the phase of the data signal from which the clock is extracted. Furthermore, no provision is made for resetting the correction loop when a predetermined amount of delay has been inserted, with the resetting done in such a manner as to make the amount of the delay apparently infinite.
It is therefore an objective of the present invention to compensate for the drift between a pair of clock signals having nearly the same frequency through a digital phase correction circuit which provides an apparently infinite amount of phase correction to align one of the clock signals with the other.
A distinct advantage of the invention is the achievement of this objective by means of a digital circuit which selects the amount of delay through a delay selection loop that operates continuously on the clock signal to be corrected through provision of a reset function.